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TMPR3927F
TOSHIBA RISC PROCESSOR
TENTATIVE
TMPR3927F
(32-bit RISC MICROPROCESSOR) 1. GENERAL DESCRIPTION
The TMPR3927F (to be called "TX3927" hereinafter) is a standard micro controller of the 32-bit RISC Microprocessor TX39 family. The TX3927 uses the TX39/H2 processor core as the CPU. The TX39/H2 processor core is a RISC CPU core Toshiba developed based on the R3000A architecture of MIPS Technologies, Inc. The TX3927 has built-in peripheral circuits which include memory controllers, a PCI controller, DMA controller, serial and parallel ports, and timer/counters.
2. FEATURES
q
TX39/H2 Processor Core * * * * * * * * The TX39/H2 is a high-performance 32-bit microprocessor core developed by Toshiba based on the R3000ATM architecture. 8kbytes of Instruction cache (2-way set associative) 4kbytes of Data cache (2-way set associative) Cache support of burst refill and cache locking functions. Supports Critical Word First Mode Incorporates MMU with translation lookaside buffer (TLB) Single cycle, 32 x 32 bit MAC unit for DSP functions Built-in Debug Support Unit (DSU)
q
SDRAM Controller * * * * * * Supports 8 channels of SDRAM, Flash (DIMM), SGRAM, or SMROM memory Supports 16M/64M/128M/256M bit SDRAM with 2/4 bank size availability Support of 16/32-bit static bus sizing on a per channel basis Supports Single Data Rate (SDR) SDRAM Supports JEDEC standard 100-pin or 168-pin DIMM sockets for SDRAM Supports JEDEC standard 100-pin DIMM sockets for Flash
q
ROM Controller * * Supports 8 channels of ROM, Page Mode ROM, Mask ROM, EPROM, E2PROM, SRAM, and Flash Memory and I/O devices. Supports memory sizes of 1M Byte to 1GByte per channel in 32-bit mode, and sizes of 1M Byte to 512M Byte per channel in 16-bit mode
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TENTATIVE * Supports independent per channel 32/16-bit static bus sizing
q
Timer/Counter * * * * 3-channel 24-bit up-counter Interval and Watchdog timer modes Support of up to 3 external (multiplexed) timer output pins Support of external input clock
q
Interrupt Controller * * Priority process of 8 internal and up to 6 external interrupt sources Support of Non Maskable interrupt (NMI)
q
PCI Controller * * * * * * * * Full compliance with PCI Local Bus Specification Revision 2.1 32-bit PCI interface at 33MHz Supports both target and initiator mode Supports zero-wait-state read and write burst transfer for target mode FIFO to minimize initial latency requirements to and from memory controller Supports auto PCI bus to local bus address space mapping Arbiter function can be enabled/disabled External interrupt function capability
q
Direct Memory Access Controller (DMAC) * * * * * Independent 4-channel DMA Supports 8/16/32-bit wide I/O devices Supports Internal/External transfer requests Supports both Dual Address and Single Address transfer modes Support of word aligned memory to memory transfers using 4-word/8-word burst reads and writes
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q
Serial I/O Ports * * * * Two-channel UART Baud rate generator and modem flow control support Supports 8-bit x 8 Transmitter FIFO Supports 13-bit x 16 (data 8-bits and status 5 -bits) Receiver FIFO
q
Parallel I/O Ports * * * Supports up to 16 bi-directional I/O pins that can be read regardless of direction or mode Independent selection of direction of pins and choice of totem-pole or open-drain outputs Support of 16-bit Flag register available as read/write register or Flag register
q q q
Power Supply:
2.5V (internal) / 3.3V (I/O)
Operating Frequency: 133MHz Package Type: 240-pin Plastic QFP
"MIPS" is the registered trade-mark of MIPS Technologies, Inc.
*The information contained herein is subject to change without notice. *TOSHIBA is continually working to improve the quality and the reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others.
*
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TENTATIVE
3. SYSTEM CONFIGURATION 3.1 3.2
TX39/H2 Processor Core I-Cache R3900A D-Cache WBU G-Bus I/F
SYSCLK A[19:2]/(Boot Signals) D[31:0]/(Boot Signals)
TMPR3927F Block Diagram
DSU
Debug[7:0]
4 channels DMAC G Bus System Bus I/F 8 channels ROMC
DMAREQ[3:0] DMAACK[3:0] DMADONE*
OE* RAS* CAS* WE* DQM[3:0] CKE SDCS*[7:0] DSF ROMCE*[7:0] OE* SWE* ACE* BWE*
8 channels SDRAMC
ACK* BUSERR* RESET*
NMI* TEST* SCAN_ENB* CLKEN
Host PCI Bridge IRC G to IM Bridge CG SIO0 IM Bus
PCI Interface INT[5:0] XIN XOUT
RXD[0] TXD[0] CTS*[0] RTS*[0]
PIO[15:0]
PIO TMR0
SCLK
TIMOUT[1] TIMIN[1] TIMOUT2 TIMIN2
TMR1 TMR2
SIO1
RXD[1] TXD[1] CTS*[1] RTS*[1]
*Note: This diagram shows the full set of functional signal connections. Due to pin multiplexing, not all of these signals will be available.
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4. PIN DESCRIPTION 4.1 PIN OUT (240-pin PQFP)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Signal VSS2 DATA[30] DATA[23] DATA[31] CE*[1] VSS CE*[0] ACE* ADDR[4] ADDR[3] ADDR[2] SYSCLK VDD2 BWE*[3] BWE*[2] VSS BWE*[1] BWE*[0] OE* SWE* SCLK RXD[0] TXD[0] RTS*[0] CTS*[0] RXD[1] TXD[1] CTS*[1] GSDAO[0] VDD2 Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Signal VSS2 VSS VDDS RTS*[1] GPCST[2] GPCST[1] GPCST[0] GDCLK GSDI GDRESET* GDBGE* PCICLK[3] VDDS VSS PCICLK[2] PCICLK[1] PCICLK[0] VSS GNT[3] GNT[2] GNT[1] GNT[0] REQ[3] REQ[2] REQ[1] REQ[0] PCIAD[31] PCIAD[30] VSS2 VDDS Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Signal VSS PCIAD[29] PCIAD[28] PCIAD[27] VSS PCIAD[26] PCIAD[25] PCIAD[24] VSS C_BE[3] VDDS IDSEL PCIAD[23] PCIAD[22] VSS PCIAD[21] PCIAD[20] PCIAD[19] VSS PCIAD[18] PCIAD[17] VDDS PCIAD[16] VSS C_BE[2] FRAME* IRDY* VSS TRDY* VDD2 Pin No. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Signal VSS2 DEVSEL* STOP* PERR* SERR* PAR C_BE[1] VSS PCIAD[15] VDDS PCIAD[14] PCIAD[13] VSS PCIAD[12] PCIAD[11] PCIAD[10] VSS PCIAD[9] PCIAD[8] VDDS C_BE[0] VSS PCIAD[7] PCIAD[6] PCIAD[5] VSS PCIAD[4] PCIAD[3] PCIAD[2] VDDS
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Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Signal VSS PCIAD[1] PCIAD[0] ACK* DMAREQ[3] DMAACK[3] DMAREQ[2] DMAACK[2] DMAREQ[0] VSS VDDS DMAACK[0] DMADONE* INT[3] INT[2] INT[1] INT[0] PIO[0] DATA[0] DATA[8] DATA[1] DATA[9] VSS DATA[2] DATA[10] DATA[3] VDDS DATA[11] DATA[4] VDD2 Pin No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Signal VSS2 DATA[12] VSS DATA[5] DATA[13] DATA[6] DATA[14] DATA[7] VDDS DATA[15] VSS DQM[0] DQM[1] ADDR[5] ADDR[6] ADDR[7] ADDR[8] VSS ADDR[9] VDDS ADDR[10] ADDR[11] ADDR[12] ADDR[13] ADDR[14] VSS ADDR[15] ADDR[16] ADDR[17] VDDS Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 Signal VSS2 XIN XOUT VDD2 VDD2 PLLVDD FILTER[0] FILTER[1] PLLVSS VSS2 NMI* SCANENB* CLKEN RESET* TEST* ADDR[18] ADDR[19] RAS* VSS CAS* SDCLK[0] SDCLK[1] SDCLK[2] VDDS SDCLK[3] SDCLK[4] VSS CKE WE* VDD2 Pin No. 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Signal VSS2 SDCS*[0] SDCS*[1] SDCS_CE*[2] SDCS_CE*[3] SDCS_CE*[4] SDCS_CE*[5] VDDS DMAACK[1] DMAREQ[1] DQM[2] VSS DQM[3] DATA[16] DATA[24] DATA[17] DATA[25] DATA[18] VSS VDDS DATA[26] DATA[19] DATA[27] DATA[20] DATA[28] DATA[21] VSS DATA[29] DATA[22] VDDS
* Active-low signal
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5. PIN FUNCTION
Name of Signal System Interface SYSCLK O System Clock Outputs a system clock with frequencies for full or half-speed bus mode depending upon programmed configuration captured at RESET*. DATA[31:0] I/O 32-bit external data bus During RESET*, the state of DATA[6:0] are used to set the configuration of the TX3927. DATA[6:0] are propagated through a transparent latch and are captured on the rising edge of RESET*. Signal is connected to internal pull-up resistor. ACK* I/O Acknowledge Signifies that there is valid data on the data bus or that a data transfer has been made. Can be driven by the TX3927 or external devices. Signal is connected to internal pull-up resistor. RESET* I Reset Initializes the TX3927. RESET* signal must remain low for a minimum of 256 SDCLK cycles to effect a valid reset. Signal is connected to internal pull-up resistor. I/O Function
Clock Signals XIN I Crystal Input Input from a crystal oscillator at 1/1, 1/2, or 1/4 of the core frequency; or input from an external crystal at 1/16 of the core frequency. XOUT O Crystal Output Asserted high if an external clock source is selected, or attached to an external crystal with a frequency of 1/16 of the core frequency. CLKEN I Clock Enable Enables internal clock generator. Should be asserted via external logic when Vdd reaches minimum specification and XIN has started and is stable. Signal is connected to internal pull-up resistor.
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Interrupt Signals NMI* I Non Maskable Interrupt Non-Maskable interrupt input. Signal is connected to internal pull-up resistor. INT[5:4] INT[3:0] I I INT [5:4] multiplexed with CTS0/RTS0 Interrupt Requests Signal is connected to internal pull-up resistor.
Timer Interface TIMER[1:0] O Timer Pulse Width Output Multiplexed with other functions. DMAREQ[3]/PIO15/TIMER[1] DMAACK[3]/PIO14/TIMER[0] DMADONE/PIO7/TIMER[0]
Memory Interface SDCLK[4:0] O SDRAM Controller Clock Signal is connected to internal pull-up resistor. RAS* O Row Address Strobe RAS* signal for the access of all synchronous memory devices. CAS* O Column Address Strobe CAS* signal for the access of all synchronous memory devices. Synchronous Memory Device Chip Select Chip select for synchronous memory devices and 100-pin DIMM Flash. SDCS[7:2] are shared with ROMCE[7:2] and are assigned by software. SDCS[7:6] are also shared with DMA REQ/ACK[1] and PIO[11:10] via software assignment. DQM[3:0] O Data Mask During a write cycle, the DQM signal functions as a Data Mask and can control every byte of the input data for SDRAMs. During a read cycle, the DQM functions as the control of the SDRAM output buffers. The DQMs also function as byte write enables to DIMM Flash during a write cycle. WE* O Write Enable Write enable signal for access of synchronous memory devices. CKE O Clock Enable Used for synchronous memory devices.
SDCS*[7:0]
O
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ACE* O ROM Address Clock Enable Enables capture of upper ten bits (multiplexed address) in an external latch. Used with ROM, SRAM, and peripheral I/O. (Only active if next upper address differs from the prior value.) SWE* O Static RAM Write Enable (Used in conjunction with ROM Controller) ADDR[19:2] O Addresses for all memory devices (During RESET*, the state of these pins are used to set the configuration of the TX3927. Pin states are propagated through a transparent latch and are captured on the rising edge of RESET*.) Signal is connected to internal pull-up resistor. OE* O Output Enable Output enable for all devices controlled by the ROM Controller and for SMROM and DIMM Flash. CE*[7:0] O ROM Chip Enable Chip selects to ROM, SRAM, FLASH and peripheral devices. Shared with SDRAM BWE*[3:0] O SDCS*[7:2] via software assignment. Signals connected to internal pull-up resistors. Data Byte Write Enable Can be Byte write enables or Byte enables during a ROMC cycle. DSF O Define Special Function Multiplexed with PIO[1] and used for SGRAM special register functions.
PCI Interface PCIAD[31..0] C_BE[3..0] PAR FRAME* TRDY* IRDY* STOP* I/O I/O I/O I/O I/O I/O I/O The 32 Bit Address and Data Buses are multiplexed on the same PCI pins. Command and Byte Enable Parity for PCIAD[31..0] and C_BE[3..0]. Even Parity Indicates beginning and duration of an transaction. Target ready Initiator ready STOP* indicates that the current Target is requesting Initiator to stop the current transaction. DEVSEL* I/O Device select Indicates that an active device has decoded its address as the target of the current access.
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REQ*[3:0] I/O Request PCI bus In internal arbiter mode, REQ*[3:0] are inputs. In external arbiter mode, REQ*[0] is an output, REQ*[1] is an interrupt output, and REQ*[3:2] are unused. GNT*[3:0] I/O Grant PCI bus In internal arbiter mode, GNT*[3:0] are outputs. In external arbiter mode, GNT*[0] is an input and GNT*[3:1] are unused. PCICLK[3:0] I/O PCICLK[0] becomes input when PCICLKEN is disabled. PCICLK[3:1] are tri-state outputs. PERR* I/O Data Parity Error Reports parity error on all transactions except Special Cycle command. ID_SEL I Initialization Device select Used as chip select during configuration read/write transaction on PCI bus. SERR* I/O System Error Reports errors for all address parity errors and data parity error on Special Cycle commands, and may optionally be used to report any other non-parity or system errors.
DMA Interface DMAREQ[3:0] I DMA Request DMA request from an external device. Signals are software assigned and shared with PIO/TIMER and SDCS_CE[7] functions. Signal is connected to internal pull-up resistor. DMAACK[3:0] O DMA Acknowledge DMA acknowledge to external devices. Signals are software assigned and shared with PIO/TIMER and SDCS_CE[6] functions. Signal is connected to internal pull-up resistor. DMADONE* I/O DMA Transfer/Chain Finished Signal is connected to internal pull-up resistor.
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SIO Interface CTS*[1:0] I SIO Clear to Send Signals are software assigned and shared with PIO/INT and serial debug GSDAO[1] functions. Signal is connected to internal pull-up resistor. RTS*[1:0] O SIO Request to Send Signals are software assigned and shared with PIO/INT and serial debug GPCST[3] functions. Signal is connected to internal pull-up resistor. RXD[1:0] I SIO Receive Data Signals are multiplexed with PIO/INT functions. Signal is connected to internal pull-up resistor. TXD[1:0] O SIO Transmit Data Signals are multiplexed with PIO/INT functions. Signal is connected to internal pull-up resistor. SCLK I External Serial Clock Signal is connected to internal pull-up resistor.
PIO Interface PIO[15:0] I/O PIO Ports All PIO signals, except 0, are shared with either DMA, INT, TIMER, Debug, or SIO functions. PIO[1] is shared with DSF, an SGRAM memory function. PIO[0] is connected to internal pull-up resistor.
Debug Interface GDCLK O Debug Clock Signal This is the clock output for the real-time debugging system. The serial monitor bus and PC trace interface signals all have their timings regulated by this debug clock. During serial monitor bus operation, this clock is half the frequency of the TX39/H2 core operating clock. GSDAO[1:0] O Serial Data and Address Output/Target PC These signals function as serial data/address outputs when operating with the serial monitor bus interface or as debug interrupt input when operating with the PC trace interface.
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GPCST[3:0] O PC Trace Status Outputs PC trace status information and serial monitor bus mode. GDRESET* I Debug Reset A reset input for the real-time debugging system. When this signal is asserted, the debug support unit (DSU) is initialized. Signal is connected to internal pull-up resistor. GDBGE* I Debugger Enable Indicates whether a real-time debugging system is connected external to the TX39/H2 core. This signal must be low when a real-time debugging system is connected or high when not connected. When DBGE* = high, the clock supplied to the DSU block is stopped. Signal is connected to internal pull-up resistor. GSDI* I Serial Data Input/ Debug Interrupt This signal functions as serial data/address input when operating with the serial monitor bus interface or as target PC input when operating with the PC trace interface. Signal is connected to internal pull-up resistor.
Others TEST* I Test Pin This signal is used as internal functional test. It should be set to high. Signal is connected to internal pull-up resistor. SCAN_ENB* I Scan Mode Test Control This signal is used as internal functional test. It should be set to high. Signal is connected to internal pull-up resistor.
Power pins and Total pin count PLL_VSS, PLL_VDD VDD2 VDDS VSS2,VSS Total Pin Count I I I Power pins at 2.5V Power pins at 3.3V Ground pins Pins: 240 pins I Power and Ground pins to internal PLL circuit.
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6. ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Ratings
Parameter Supply voltage
Symbol
VDDS VDD2
Rating
-0.3 4.5 -0.3 ~ 3.6
Unit
V
Input voltage RXD[1:0], CTS[1:0], PCIAD[31:0], PCICLK[3:0], GNT[3:0], REQ[3:0], C_BE[3:0], IDSEL, FRAME*, IRDY*, TRDY*, DEVSEL*, STOP*, PERR*, SERR*, PAR Other inputs
VIN1
-0.3 6.7V
V
VIN2 Storage temperature Maximum power dissipation TSTG PD
-0.3 VDDS + 0.3V -40 125 2.0
V C W
Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in possible injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating will ever be exceeded.
6.2
Recommended Operating Conditions
Parameter
Symbol
I/O Internal VDDS VDD2 Tc
Condition
Min. 3.0 2.3 0
Max. 3.6 2.7 70
Unit V V C
Supply voltage
Operating case temperature
Note: The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device, is used under conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC and DC values, etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to.
6.3
DC Characteristics
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6.3.1 DC characteristics of pins other than PCI interface pins
(Tc = 0 70C, V = 3.3V 0.3V, V = 2.5V 0.2V, V = 0V) DDS DD2 SS Parameter Low-level input voltage
Symbol
VIL1 VIL2 VIH1 VIH2 IOL1 IOL2
Condition
RXD[1:0], CTS[1:0] RXD[1:0], CTS[1:0] RXD[1:0], CTS[1:0] RXD[1:0], CTS[1:0] (1) V L = 0.4V O (2) V L = 0.4V O
Min.
Max. VDD x 0.2
Unit
V
0.8 VDDSx 0.8 2.0 VDDSx 0.3 5.5 8 16 mA mA V
High-level input voltage
Low-level output current
High-level output current
IOH1 IOH2
(1) V H = 2.4V O (2) V H = 2.4V O
-8 -16
mA mA
Operating current I/O Internal Input leakage current
IDDS IDD2 IIH IIL RST
(3) f=133MHz, VDDS = 3.6V (3) f=133MHz, VDDS = 2.7V -10 -10 50
120 420 10 10 300
mA mA A A
Pullup Resistor (1) (2) (3)
: Other signals, Excluding (2) : ADDR[ 19:5], SDCLK[4:0], DQM[3:0], DATA[31:0], CAS*, RAS*, CKE, WE*, OE*, SYSCLK, GDCLK, ACK* f: CPU frequency
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6.3.2 DC characteristics of PCI interface pins
(Tc = 0 70C, V = 3.3V 0.3V, V = 2.5V 0.2V, V = 0V) DDS DD2 SS Parameter Low-level input voltage High-level input voltage
Symbol
VIL3 VIH3
Condition
Min. -0.5 VDDS x 0.5
Max. VDDS x 0.3 5.5
Unit V V
Output High Voltage Output Low Voltage Input leakage current
VO H VO L IIH IIL
IOUT = -2mA IOUT = 3mA, 6mA 0 < V < 5V IN
VDDS x 0.9 VDDS x 0.1 -10 -10 10 10
V V A A
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6.4
6.4.1
Crystal Oscillator Characteristics
Recommended oscillator conditions
TMPR3927F XIN ROUT XOUT
CIN
Parameter Crystal Oscillator frequency Output register External condenser Clock generator Rising time Falling time f IN ROUT
X'tal
Symbol 6.25~8.33 10 12
COUT
Recommended value Unit MHz M pF
CIN,COUT
tr tf
5(1) 5(1)
ns ns
(1) For a reference. Ask clock generator manufacture.
6.4.2
Recommended input clock conditions (when 2-multiply)
Parameter Input Clock Frequency
Symbol f IN
Recommended Value 50 ~ 66.67
Unit MHz
Note: When 2-multiply, the external clock should input to the XIN pin. Then the XOUT pin must be left open.
6.4.3
Electrical characteristics
(Tc = 0 70C, V = 3.3V 0.3V, V = 2.5V 0.2V, V = 0V) DDS DD2 SS Parameter Oscillation start time Symbol tSTA Condition f=6.25 8.75MHz MIN. TYP. 1 MX A. 10 Unit ms
6.5
PLL Filter Circuit
The following filter circuit is recommended for the PLL filter using the pins LP (Filter0) and AGS (Filter1).
Filter0
Filter1
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Symbol External Capacitor
Symbol CFilter
Recommended Value 1800 (using 16x divider) 220 (using 2x divider)
Unit pF pF
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6.6
6.6.1
AC Characteristics (of pins other than PCI interface pins)
Table of AC characteristics
(Tc = 0 70C, V = 3.3V 0.3V, V = 2.5V 0.2V, V = 0V, CL = 50pF) DDS DD2 SS
Symbol tsys t
sysh
Signal
SYSCLK/SDCLK[4:0] SYSCLK SYSCLK/SDCLK[4:0] SYSCLK (1) (1) (2) (2) DATA[31:0], ACK* DATA[31:0], ACK* Cycle Time
Description
Min 15 30 5 12
Max
Unit ns ns ns ns
Cycle Time (Half-speed bus mode) Min High/Low Level Min Half-Speed High/Low Level Output Delay Output Hold Input Setup Input Hold Data Active to Hi-Z Data Hi-Z to Active
tsysm tsysmh td toh tsu tih tdaz t
dza
7 1 7 0 7 1
ns ns ns ns ns ns
(1) ACK*, DATA[31:0], ROMCE[7:0]*, OE*, ACE*, SWE*, BWE[3:0]*, ADDR[19:2], DMAACK[3:0], DMADONE*, PIO[15:0], TIMER[1:0] (2) ACK*, DATA[31:0], NMI*, INT[5:0], DMAREQ[3:0], DMADONE*, PIO[15:0]
6.6.2
SDRAM Interface AC characteristics
(Tc = 0 70C, V = 3.3V 0.3V, V = 2.5V 0.2V, V = 0V, CL = 50pF for SDCLK[4:0]) DDS DD2 SS 50pF 100pF Min 15 5 7 8 1 7 2 0 7 1 1 1 7 2 0 7 1 8 10 1 7 2 0 7 Max 150pF Min 15 5 9 12 Max Unit ns ns ns ns ns ns ns ns ns ns
Symbol tsdclk tsdclkm tsd tsdd tsoh tssu1 tssu2 tsih tsdaz tsdza
Signal SDCLK[4:0]/SYSCLK SDCLK[4:0]/SYSCLK
3
Description Cycle Time Minimum High/Low Level Output Delay Output Delay Output Hold Input Setup (Internal clock) Input Setup (Pin feed-back clock) Input Hold Data Active to Hi-Z Data Hi-Z to Active
Min 15 5
Max
DATA[31:0]
4
DATA[31:0] DATA[31:0] DATA[31:0] DATA[31:0] DATA[31:0]
(3) SDCS[7:0], RAS*, CAS*, WE*, CKE, OE*, DSF, ADDR[19:5], DQM[3:0] (4) SDCS[7:0], RAS*, CAS*, WE*, CKE, OE*, DSF, ADDR[19:5], DQM[3:0], DATA[31:0]
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6.7
6.7.1
AC Characteristics (of PCI interface pins)
AC characteristics table
(PCI_CLK speed = 33MHz, Tc = 0 70C, V = 5.0V 0.25V, V = 0V, CL = 50pF) DD SS Symbol tcyc thigh tlow tval tval(ptp) ton toff tsu tsu(ptp) th trst trst-clk trst-off Signal PCI_CLK cycle time PCI_CLK high time PCI_CLK low time PCI_CLK slew rate PCI_CLK to signal valid delay - bused signals PCI_CLK to signal valid delay - point to point signals Float to active delay Active to float delay Input set up time to PCI_CLK - bused signals Input set up time to PCI_CLK - point to point signals Input hold time from PCI_CLK Reset active time after power stable Reset active time after PCI_CLK stable Reset active to output float delay 7 12 0 1 100 40 Description Min. 30 11 11 1 2 2 2 28 4 11 12 Max. Unit ns ns ns V/ns ns ns ns ns ns ns ns ms us ns
Symbol
Parameter Switching Current High
Condition
0Min. -44 -44+( Vout -1.4)/ 0.024
Max. 0.8
Unit mA mA
IOH (AC)
Eqt'n A -142 95 Vout / 0.023 Eqt'n B 206 -25+(Vin+1)/ 0.015 1 1 5 5 mA mA V/ns V/ns mA mA mA
(Test Point)
Vout = 3.1 Vout > 2.2 2.2 > Vout > 0.55 0.71>Vout >Vcc
IOL (AC)
Switching Current Low
(Test Point)
Vout = 0.71 -5 ICL slew r slew f
Low Clamp Output Output Rise Slew Rate Output Fall Slew Rate
Please refer to the PCI Local Bus Specification Revision 2.2 for more information.
TAEC_rev4_11-Jan-2000 19/22
TMPR3927F
TENTATIVE
6.8
6.8.1
Timing Diagrams
Definition of AC characteristics
tsym, tsysh tsysm, tsysmh tsysm, tsysmh td SYSCLK Output tsu SYSCLK Input
toh tdaz
tdza
tih
6.8.2
Definition of AC characteristics (of PCI pins) ton tval tcyc toff 0.4Vdd 0.4Vdd 0.4Vdd tHigh 0.4Vdd tLow
PCICLK Output Delay Tri-state Output Delete
tsu PCICLK. Input 0.4Vdd Valid
th
0.4Vdd
TAEC_rev4_11-Jan-2000 20/22
TMPR3927F
TENTATIVE
7. PACKAGE DIMENSION
QFP240-P-3232-0.5 Unit: mm
TAEC_rev4_11-Jan-2000 21/22
TMPR3927F
TENTATIVE QFP240-P-3232-0.5 Unit: mm
TAEC_rev4_11-Jan-2000 22/22

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